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1/11 september 2002 n 16mhz toggle rate (typ.) at v dd - v ss = 10v n gated inputs n quiescent current specified up to 20v n 5v, 10v and 15v parametric ratings n input leakage current i i = 100na (max) at v dd = 18v t a = 25c n 100% tested for quiescent current n meets all requirements of jedec jesd13b "standard specifications for description of b series cmos devices" description hcf4095b is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in dip and sop packages. hcf4095b is j-k master-slave flip-flops featuring separate and gating of multiple j and k inputs. the gated j-k input control transfers information into the master section during clocked operation. information on the j-k inputs is transferred to the q and q outputs on the positive edge of the clock pulse. set and r eset i nputs (active high) are provided for asynchronous operation. hcf4095b gated j-k master slave flip-flop pin connection order codes package tube t & r dip HCF4095BEY sop hcf4095bm1 hcf4095m013tr dip sop
hcf4095b 2/11 input equivalent circuit pin description truth table : synchronous operation (s=0 r=0) (*) : j=j1 ? j2 ? j3, k=k1 ? k2 ? k3 truth table : asynchronous operation (j and k dont care) (*) : l = vss, h = vdd pin no symbol name and function 3, 4, 5 j1 to j3 j inputs 11, 10, 9 k1 to k3 k inputs 8 q q output 6q q output 13 set (s) set inputs(active high) 2 reset (r) reset inputs(active high) 12 clock clock inputs 1 nc not connected 7 v ss negative supply voltage 14 v dd positive supply voltage inputs before positive clock transition outputs after positive clock transition j* k* q q l l no change lhlh hlhl h h toggles inputs before positive clock transition outputs after positive clock transition srqq l l no change lhlh hlhl hhl l
hcf4095b 3/11 functional diagram logic diagram
hcf4095b 4/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. all voltage values are referred to v ss pin voltage. recommended operating conditions dc specifications symbol parameter value unit v dd supply voltage -0.5 to +22 v v i dc input voltage -0.5 to v dd + 0.5 v i i dc input current 10 ma p d power dissipation per package 200 mw power dissipation per output transistor 100 mw t op operating temperature -55 to +125 c t stg storage temperature -65 to +150 c symbol parameter value unit v dd supply voltage 3 to 20 v v i input voltage 0 to v dd v t op operating temperature -55 to 125 c symbol parameter test condition value unit v i (v) v o (v) |i o | ( m a) v dd (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. i l quiescent current 0/5 5 0.02 1 30 30 m a 0/10 10 0.02 2 60 60 0/15 15 0.02 4 120 120 0/20 20 0.04 20 600 600 v oh high level output voltage 0/5 <1 5 4.95 4.95 4.95 v 0/10 <1 10 9.95 9.95 9.95 0/15 <1 15 14.95 14.95 14.95 v ol low level output voltage 5/0 <1 5 0.05 0.05 0.05 v 10/0 <1 10 0.05 0.05 0.05 15/0 <1 15 0.05 0.05 0.05 v ih high level input voltage 0.5/4.5 <1 5 3.5 3.5 3.5 v 1/9 <1 10 7 7 7 1.5/13.5 <1 15 11 11 11 v il low level input voltage 4.5/0.5 <1 5 1.5 1.5 1.5 v 9/1 <1 10 3 3 3 13.5/1.5 <1 15 4 4 4 i oh output drive current 0/5 2.5 <1 5 -1.36 -3.2 -1.15 -1.1 ma 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4 i ol output sink current 0/5 0.4 <1 5 0.44 1 0.36 0.36 ma 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 0/15 1.5 <1 15 3.0 6.8 2.4 2.4
hcf4095b 5/11 the noise margin for both "1" and "0" level is: 1v min. with v dd =5v, 2v min. with v dd =10v, 2.5v min. with v dd =15v dynamic electrical characteristics (t amb = 25c, c l = 50pf, r l = 200k w , t r = t f = 20 ns) (*) typical temperature coefficient for all v dd value is 0.3 %/c. i i input leakage current 0/18 any input 18 10 -5 0.1 1 1 m a c i input capacitance any input 5 7.5 pf symbol parameter test condition value (*) unit v dd (v) min. typ. max. t plh t phl propagation delay time 5 250 500 ns 10 100 200 15 75 150 t plh t phl propagation delay time (set or reset) 5 150 300 ns 10 75 150 15 50 100 t tlh t thl transition time 5 100 200 ns 10 50 100 15 40 80 f cl maximum clock input frequency 5 3.5 7 mhz 10 8 16 15 12 24 t w clock pulse width 5 140 70 ns 10 60 30 15 40 20 t r, t f clock input rise or fall time 5 15 m s 10 5 15 5 t w set or reset pulse width 5 200 100 ns 10 100 50 15 50 25 t setup data setup time 5 400 200 ns 10 160 80 15 100 50 symbol parameter test condition value unit v i (v) v o (v) |i o | ( m a) v dd (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max.
hcf4095b 6/11 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 200k w r t = z out of pulse generator (typically 50 w ) waveform : propagation delay, transition and setup time
hcf4095b 7/11 waveform : clock pulse, rise and fall time typical application: t-type flip-flop
hcf4095b 8/11 typical application: synchronous binary divide by ten counter truth table note: in all units the set and reset are connected to v ss . stateqaqbqcqd 0llll 1hlll 2lhll 3hhll 4llhl 5hlhl 6lhhl 7hhhl 8lllh 9hllh
hcf4095b 9/11 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100 plastic dip-14 mechanical data p001a
hcf4095b 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45? (typ.) d 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.68 0.026 s ? (max.) so-14 mechanical data po13g 8
hcf4095b 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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